In the fabrication of integrated circuit devices, logic products are often produced using silicide operations in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited on a silicon wafer or a silicon layer and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
As the dimensions within integrated circuits have grown ever smaller, solutions have had to be found to problems relating to misalignment of successive mask patterns relative to one another during operation. Therefore approaches such as salicide (self-aligned silicide) operation is developed to take advantage of the fact that certain metals react when heated in contact with silicon to form conductive silicides but do not react with silicon oxide. Thus, oxide spacers on the vertical walls of the gate pedestal could be used to provide the necessary small, but well-controlled, separation between the source and drain contacts and the gate contact.
Although the salicide operation made possible significant reductions in device size, as devices shrank even further, other issue emerges. For example, as the devices become smaller, the source/drain regions become shallower and salicide induces damage to the subjacent junctions. For example, metal spiking, where the metal diffuses unevenly into the silicon wafer or silicon layer is induced. Consequently, junction leakage is likely to occur. There is therefore a need in the semiconductor processing art to develop a method for forming improved salicides having reduced parasitic electrical leakage while maintaining a low sheet resistance.